IEEE UofT ASIC Team - Introduction
The IEEE UofT ASIC Team is a specialized project team within the IEEE University of Toronto Student Branch, dedicated to giving undergraduate students real, hands-on experience with integrated circuit (IC) design. While most ECE students encounter IC concepts in class, they are rarely given the chance to actually build and fabricate their own chips. The ASIC Team bridges that gap by leveraging open-source tools and the Free and Open Source Silicon (FOSSi) ecosystem, enabling students to design, verify, and tape out real silicon.
What Is This HackathonThis week-long hackathon is centered around taking an idea from concept to hardware-ready design. We want to extend the opportunities for students at the University of Toronto, and this hackathon is a way for us to allow a lot of students to get exposure to tooling that could produce and create real silicon!
Throughout the hackathon participants will prototype digital and/or analog systems and push them through real-world workflows that mirror how chips are built in industry, from writing synthesizable code to running it through a realistic synthesis flow.
Requirements
Full hackathon theme document can be found here
Junior Division
The Junior Division is open only to first-year or non-ECE or non-EngSci students.
Junior submissions will be synthesized and implemented on an FPGA, specifically the DE1-SoC, to simplify the hardware bring-up and verification process. Competitors are encouraged to take advantage of the board’s built-in resources, including on-chip memory, ADCs, and other available peripherals.
The focus in this division is learning, experimentation, and demonstrating how hardware acceleration can outperform CPU-based approaches.
Senior Division
The Senior Division is open to all participants.
Senior submissions must be fully synthesizable Tiny Tapeout designs that meet all size and interface constraints. Because fabricated ICs can take months to return, designs should emphasize safety, robustness, and correctness. A strong submission is one that is carefully verified and unlikely to require re-fabrication.
This division rewards thoughtful hardware architecture, reliability, and designs that fully embrace the strengths (and responsibilities) of custom silicon.
What to Submit
A Github repository
- Junior Division - FPGA Synthesizeable HDL
- Senior Division - Github actions should show green checkmarks and the HDL should be fully synthesizeable for a tiny tapeout IC - More information on the tiny tapeout template can be found here
Furthermore, at least one of the members of each team must present their design in front of the judges on the closing day (Feb 22nd, 2026) at their assigned time slots.
Prizes
First Place - ASIC
Alongside some cash, you will get a TinyTapeout credit!
Second Place - ASIC
Win cash and get a tapeout credit!
Third Place - ASIC
Win cash and get a tapeout credit!
First Place - FPGA
Honourable Mention - FPGA
Congratulations are in order for the honourable mention projects!
Honourable Mention - ASIC
Congratulations are in order for the honourable mention projects!
Devpost Achievements
Submitting to this hackathon could earn you:
Judges
Vraj Prajapati
ASIC Team
Judging Criteria
-
Technical Fidelity
Project integrates many technically complex components together into a fully functional project. -
Demo / Presentation
Demo is extensible and indefinitely repeatable. Presentation demonstrates depth in the engineering process to the final design. -
Idea Originality (Creativity)
Idea is original and described in great detail. Idea is useful in that it solves a problem, provides a service, or enables a significant function. -
Feasability
Design can be fully synthesized and placed on a Caravel harness for tapeout. -
Verification
Design possesses a well-thought out testbench which covers key functionality of your design.
Questions? Email the hackathon manager
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