Ray-Sphere Intersection Engine

Simulation waveform of the complete, pipelined ray-sphere intersection engine.

Inspiration

Our inspiration for the topic of where FPGA/ASIC designs can outperform a CPU came from the way GPUs accelerate graphics processing. CPUs struggle to compute data like GPUs for arithmetic-heavy tasks such as ray tracing. By exploring the root computation behind ray tracing, we identified ray-sphere intersection testing as a core process and built our project around the acceleration of that in hardware.

What it does

This project computes ray-sphere intersections in hardware using the inputs of ray origin and direction, alongside sphere center and radius. It outputs a hit or a miss signal, alongside the intersection distance. The design achieves one result per clock cycle, outperforming a CPU.

How we built it

We implemented the Ray-Sphere Intersection Engine in Verilog using fixed-point arithmetic to efficiently evaluate the quadratic discriminant used in ray-sphere intersection tests. We also developed a structured testbench that generates full frames, tracks hits/misses, and dumps waveforms for verification.

Challenges we ran into

The major challenge we ran into was debugging and correctly generating the simulation waveforms for verification. The "vcd2wavedrom" consistently crashed when given signal names such as "sph_cx[0]" because it interpreted [0] as bit indexing rather than an array element. We corrected this by modifying our "$dumpvars" configuration to exclude array signals from the output.

Accomplishments that we're proud of

We are proud that we have built a fully pipelined hardware engine that is modular, scalable, and verified. We demonstrated how arithmetic algorithms can be accelerated through hardware dataflow and clearly illustrated the advantages of FPGA-based computations for arithmetic-heavy workloads.

What we learned

We learned that performance can be gained from more than raw clock speed and that parallelism and pipelining are also key. We also gained experience in hardware verification, timing alignment, and developed an appreciation of the importance pf building a software reference for mathematical verification.

What's next for Ray-Sphere Intersection Engine

Next, we plan to measure the time per intersection calculation and compare it to a CPU implementation to validate our hardware advantage. From there, we will duplicate intersection engines to utilize parallelism and increase our output per second further. Ultimately, our goal is to scale this project to a full ray tracing accelerator with shading capabilities.