ASIC-RayForge

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  Concept PCB

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  VGA Demodulator and Driver PCB

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Inspiration

Modern ray tracing is the exclusive domain of high-end GPUs and sprawling software stacks. We became fixated on implementing photorealistic rendering directly in silicon, stripped of every software abstraction.

What it does

ASIC-RayForge is a complete, end-to-end ray tracing pipeline on a single chip. A scene is authored through a Bluetooth-connected GUI running on an nRF52840, transmitted over UART to the ASIC. It loads the scene into memory and begins tracing rays against a collection of spheres, computing up to 8 bounces of reflection per ray. To sustain a steady 60fps output, the chip dynamically adjusts ray depth at runtime, delivering the final rendered image directly to a VGA monitor over a custom PCB with no external display drivers required.

How we built it

The entire pipeline was designed in Verilog, targeting the Tiny Tapeout platform. Because silicon area is a scarce, all arithmetic was implemented in fixed-point to keep the design compact enough to synthesize within the available footprint. The hardware handles ray generation, sphere intersection, shading, and multi-bounce reflections. On the software side, a custom Bluetooth editor allows a scene to be composed on a phone and reflected on the monitor in real time. The full design was validated against a Verilator testbench before tapeout submission.

The "Wall" (Challenges)

Collaborative hardware development is a unique challenge. We built a generalized Verilator testbench early on so that team members could develop and test modules independently without destabilizing each other's work. With nearly zero on-chip memory available due to Tiny Tapeout constraints, the approach to scene storage required fundamental rethinking. Fixed-point arithmetic introduced a third challenge, as small rounding errors in the first bounce compound across eight reflections. Generating a stable VGA signal directly from chip I/O without intermediate display hardware also required far more iteration than anticipated.

What we’re proud of

Seeing a multi-bounce reflection pipeline produce correct output in simulation brought us immense satisfaction. There is also something fundamentally elegant about a custom PCB driving a VGA monitor directly from our own silicon, with no intermediate chips in the signal path.

What we learned

Graphics hardware presents a verification challenge that purely digital designs do not. A waveform viewer cannot indicate whether shading is correct, and we learned that mathematical units must be rigorously tested before integration. We also found that parametric design was critical to keep the ASIC's footprint within the allotted area.

What’s next?

The immediate goal is to extend the geometry model, adding triangle support for polygon meshes and implicit surfaces for mathematically defined shapes. The core pipeline is in place, and the natural endpoint is fabricating our design on silicon.

Built With

• c++
• systemverilog
• verilator
• verilog