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MIPS (Microprocessor without Interlocked Pipelined Stages) is a RISC CPU architecture used in systems like SGI O2 and Octane systems, Nintendo N64 as well as the Sony Playstation, Playstation 2 and Playstation Portable.
General Registers
| Name
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Number
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Function
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Callee must preserve?
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| $zero
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$0
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constant 0
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n/a
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| $at
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$1
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assembler temporary
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no
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| $v0–$v1
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$2–$3
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values for function returns and expression evaluation
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no
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| $a0–$a3
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$4–$7
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function arguments
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no
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| $t0–$t7
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$8–$15
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temporaries
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no
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| $s0–$s7
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$16–$23
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saved temporaries
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yes
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| $t8–$t9
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$24–$25
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temporaries
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no
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| $k0–$k1
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$26–$27
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reserved for OS kernel
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no
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| $gp
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$28
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global pointer
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yes
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| $sp
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$29
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stack pointer
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yes
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| $fp/$s8
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$30
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frame pointer
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yes
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| $ra
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$31
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return address
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n/a
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Note: All except registers on the MIPS except $zero, HI and LO are general registers; the listed usage is per convention and not enforced by the processor or the assembler. The register name $s8 is a synonym for $fp used in some assemblers, in systems where the frame pointer is not regularly used.
Arithmetic Registers
| Register
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Multiplication
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Division
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| HI
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Multiplicand Upper word
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Quotient
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| LOW
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Multiplicand Lower word
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Remainder
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Coprocessor 0 Registers
| Name
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Number
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Function
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Callee must preserve?
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| c0_index
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cop0 $0
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TLB entry index register
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n/a
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| c0_random
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cop0 $1
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TLB randomized access register
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n/a
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| c0_entrylo
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cop0 $2
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Low-order word of "current" TLB entry
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n/a
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| c0_context
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cop0 $4
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Page-table lookup address
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n/a
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| c0_vaddr
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cop0 $8
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Virtual address associated with certain exceptions
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n/a
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| c0_entryhi
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cop0 $10
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High-order word of "current" TLB entry
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n/a
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| c0_status
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cop0 $12
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Processor status register
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n/a
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| c0_cause
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cop0 $13
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Exception cause register
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n/a
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| c0_epc
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cop0 $14
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PC at which exception occurred
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n/a
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Instruction fields
| Field
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Size
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Position
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Op Types
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Description
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| op
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6
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26-31
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R, I, J
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opcode for the instruction or group of instructions.
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| rs
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5
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21-25
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R, I
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Source register for store operations, destination for all other operations.
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| rt
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5
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16-20
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R, I
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First operand register.
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| rd
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5
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11-15
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R
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Second operand register.
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| shift
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5
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6-10
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R
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Immediate operand for shift and rotate instructions.
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| func
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6
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0-5
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R
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Extended opcode.
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| imm
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16
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0-15
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I
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Half-word immediate operand.
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| address
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0-25
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J
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26-bit address field for unconditional jump operations.
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Addressing modes
| Type
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Assembly Format
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Opcode format
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Comments
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| Register
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inst rs, rd, rt
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op rs, rd, rt, shift, func
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The opcode represents a group of operations rather than a specific instruction; the func field contains the actual operation. The shift field is only used in shift and rotate operations.
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| Immediate (I-type)
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inst rs, rt, imm
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opcode rs, rt, imm
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Immediate operation use a 16-bit immediate value from the instruction word itself.
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| Load (I-type)
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inst rs, imm(rt)
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op rs, rt, imm
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Load/Store operations are a special case of immediate, where the offset is the immediate operand.
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| Store (I-type)
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inst rs, offset(rt)
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op rs, rt, imm
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Unlike in most other operations, the rs register is the data source.
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| Cond. Branch(I-type)
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inst rs, rt, label
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op rs, rt, imm
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Conditional branches have a 16-bit relative range.
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| Jump {J-type)
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inst label
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op address
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the J and JAL operations have a 26-bit relative range.
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Note: The assembly formats given are those from the official MIPS Technologies documentation. Other assemblers (e.g., gas) may use different formats.
See Also
Articles
References
