Pinned Loading

1. FinancialAccleration FinancialAccleration Public

   Collection of my assorted garbage with FPGA and low-latency deployments for market-related items.

   Verilog

2. FPGAtors-SystemVerilog-Tutorial FPGAtors-SystemVerilog-Tutorial Public

   My files both written live and used (side scripts) for the SystemVerilog tutorial part 2.

   SystemVerilog

3. ChesapeakeArchitecture ChesapeakeArchitecture Public

   RISCV in SystemVerilog Summer Project

   SystemVerilog

4. janestreet/hardcaml janestreet/hardcaml Public

   Hardcaml is an OCaml library for designing hardware.

   OCaml 985 57