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1. RISC-V-3-Stage-Core RISC-V-3-Stage-Core Public

   A fully functional 3-stage pipelined RISC-V CPU implementation in SystemVerilog. This project implements a complete RISC-V instruction set architecture processor with memory hierarchy, cache system…

   SystemVerilog 1

2. AXI-Lite AXI-Lite Public

   This AXI-Lite repository is a simplified subset of the ARM AMBA AXI protocol for memory-mapped register and control interfaces. It uses handshaking on each channel, supports only single-beat (non-b…

   SystemVerilog

3. N-Body-Simulation N-Body-Simulation Public

   A high-performance GPU-accelerated N-body gravitational simulation implementing the Barnes-Hut algorithm for O(N log N) complexity. This project uses CUDA development techniques and parallel algori…

   Cuda 2

4. Gshare Gshare Public

   SystemVerilog implementation of the gshare branch predictor. XOR-based indexing to access PHT of 128 2-bit saturating counters. Includes separate prediction and training interfaces to support specu…

   SystemVerilog

5. Powershell Powershell Public

   A custom command-line shell for Windows built from scratch in C++, featuring a suite of built-in filesystem and text manipulation commands

   C++

6. Gameboy-Advance Gameboy-Advance Public

   Gameboy Advance for MiSTer Platform ported for development on AUP-ZU3 FPGA.

   VHDL