unisimdassembler Code changeshttps://sourceforge.net/p/unisimdassembler/code/Recent changes to Code repository in unisimdassembler projectenWed, 20 Nov 2024 19:47:59 -0000add support for 128-bit ARM SVE (x1/x2)https://sourceforge.net/p/unisimdassembler/code/ci/f11583afbee2a3b953831d8b46b39bfb8fcfbee4/<div class="markdown_content"><p>add support for 128-bit ARM SVE (x1/x2)<br/><a href="/p/unisimdassembler/code/ci/f11583afbee2a3b953831d8b46b39bfb8fcfbee4/">View Changes</a></p></div>VectorChiefWed, 20 Nov 2024 19:47:59 -0000https://sourceforge.net/p/unisimdassembler/code/ci/f11583afbee2a3b953831d8b46b39bfb8fcfbee4/clean up SIMD test output formattinghttps://sourceforge.net/p/unisimdassembler/code/ci/e3aae7f2bb86d7c98f35ee68c34fed6222ad5299/<div class="markdown_content"><p>clean up SIMD test output formatting<br/><a href="/p/unisimdassembler/code/ci/e3aae7f2bb86d7c98f35ee68c34fed6222ad5299/">View Changes</a></p></div>VectorChiefWed, 24 Apr 2024 18:36:52 -0000https://sourceforge.net/p/unisimdassembler/code/ci/e3aae7f2bb86d7c98f35ee68c34fed6222ad5299/add initial predicated SIMD backendshttps://sourceforge.net/p/unisimdassembler/code/ci/c87627f17ea3194755c9d7a6d92e2418702044b7/<div class="markdown_content"><p>add initial predicated SIMD backends<br/><a href="/p/unisimdassembler/code/ci/c87627f17ea3194755c9d7a6d92e2418702044b7/">View Changes</a></p></div>VectorChiefWed, 24 Apr 2024 18:36:52 -0000https://sourceforge.net/p/unisimdassembler/code/ci/c87627f17ea3194755c9d7a6d92e2418702044b7/add signed/unsigned 32/64-bit SIMD div/remhttps://sourceforge.net/p/unisimdassembler/code/ci/0d2eaed6275c95ea8c2b327680ee79e5522d9ee2/<div class="markdown_content"><p>add signed/unsigned 32/64-bit SIMD div/rem<br/><a href="/p/unisimdassembler/code/ci/0d2eaed6275c95ea8c2b327680ee79e5522d9ee2/">View Changes</a></p></div>VectorChiefWed, 24 Apr 2024 18:36:52 -0000https://sourceforge.net/p/unisimdassembler/code/ci/0d2eaed6275c95ea8c2b327680ee79e5522d9ee2/add configurable scaled-indexed addressing modeshttps://sourceforge.net/p/unisimdassembler/code/ci/b087645bbcc6915d843745e477563dfff6ca9e8b/<div class="markdown_content"><p>add configurable scaled-indexed addressing modes<br/><a href="/p/unisimdassembler/code/ci/b087645bbcc6915d843745e477563dfff6ca9e8b/">View Changes</a></p></div>VectorChiefWed, 24 Apr 2024 18:36:52 -0000https://sourceforge.net/p/unisimdassembler/code/ci/b087645bbcc6915d843745e477563dfff6ca9e8b/clean up signed/unsigned SIMD convertershttps://sourceforge.net/p/unisimdassembler/code/ci/055962a6625e0873573ff04b32de512995c1fe61/<div class="markdown_content"><p>clean up signed/unsigned SIMD converters<br/><a href="/p/unisimdassembler/code/ci/055962a6625e0873573ff04b32de512995c1fe61/">View Changes</a></p></div>VectorChiefWed, 28 Feb 2024 20:22:50 -0000https://sourceforge.net/p/unisimdassembler/code/ci/055962a6625e0873573ff04b32de512995c1fe61/add unsigned fp-to-int SIMD convertershttps://sourceforge.net/p/unisimdassembler/code/ci/9d2ae6bd20410637e0ccbd240e68c9c61ad567f6/<div class="markdown_content"><p>add unsigned fp-to-int SIMD converters<br/><a href="/p/unisimdassembler/code/ci/9d2ae6bd20410637e0ccbd240e68c9c61ad567f6/">View Changes</a></p></div>VectorChiefWed, 28 Feb 2024 20:22:50 -0000https://sourceforge.net/p/unisimdassembler/code/ci/9d2ae6bd20410637e0ccbd240e68c9c61ad567f6/clean up unsigned SIMD convertershttps://sourceforge.net/p/unisimdassembler/code/ci/9d03634771989f0c57ad035f79d96415ba17a063/<div class="markdown_content"><p>clean up unsigned SIMD converters<br/><a href="/p/unisimdassembler/code/ci/9d03634771989f0c57ad035f79d96415ba17a063/">View Changes</a></p></div>VectorChiefWed, 21 Feb 2024 19:53:14 -0000https://sourceforge.net/p/unisimdassembler/code/ci/9d03634771989f0c57ad035f79d96415ba17a063/add unsigned int-to-fp SIMD convertershttps://sourceforge.net/p/unisimdassembler/code/ci/5243f02b2e29707d53e948a16ef2b5b53e0dbf3c/<div class="markdown_content"><p>add unsigned int-to-fp SIMD converters<br/><a href="/p/unisimdassembler/code/ci/5243f02b2e29707d53e948a16ef2b5b53e0dbf3c/">View Changes</a></p></div>VectorChiefWed, 14 Feb 2024 20:48:33 -0000https://sourceforge.net/p/unisimdassembler/code/ci/5243f02b2e29707d53e948a16ef2b5b53e0dbf3c/rename internal Te** registers to TE** on RISCshttps://sourceforge.net/p/unisimdassembler/code/ci/f43ee37be37191cd19bcc5269d068765daae6e3f/<div class="markdown_content"><p>rename internal Te<strong> registers to TE</strong> on RISCs<br/><a href="/p/unisimdassembler/code/ci/f43ee37be37191cd19bcc5269d068765daae6e3f/">View Changes</a></p></div>VectorChiefWed, 14 Feb 2024 20:48:33 -0000https://sourceforge.net/p/unisimdassembler/code/ci/f43ee37be37191cd19bcc5269d068765daae6e3f/