https://sourceforge.net/p/unisimdassembler/code/2024-11-20T19:47:59.908000ZRecent changes to Code repository in unisimdassembler project2024-11-20T19:47:59.908000Z2024-11-20T19:47:59.908000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/f11583afbee2a3b953831d8b46b39bfb8fcfbee4/

<div class="markdown_content"><p>add support for 128-bit ARM SVE (x1/x2)<br/><a href="/p/unisimdassembler/code/ci/f11583afbee2a3b953831d8b46b39bfb8fcfbee4/">View Changes</a></p></div>

2024-04-24T18:36:52.881000Z2024-04-24T18:36:52.881000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/e3aae7f2bb86d7c98f35ee68c34fed6222ad5299/

<div class="markdown_content"><p>clean up SIMD test output formatting<br/><a href="/p/unisimdassembler/code/ci/e3aae7f2bb86d7c98f35ee68c34fed6222ad5299/">View Changes</a></p></div>

2024-04-24T18:36:52.873000Z2024-04-24T18:36:52.873000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/c87627f17ea3194755c9d7a6d92e2418702044b7/

<div class="markdown_content"><p>add initial predicated SIMD backends<br/><a href="/p/unisimdassembler/code/ci/c87627f17ea3194755c9d7a6d92e2418702044b7/">View Changes</a></p></div>

2024-04-24T18:36:52.855000Z2024-04-24T18:36:52.855000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/0d2eaed6275c95ea8c2b327680ee79e5522d9ee2/

<div class="markdown_content"><p>add signed/unsigned 32/64-bit SIMD div/rem<br/><a href="/p/unisimdassembler/code/ci/0d2eaed6275c95ea8c2b327680ee79e5522d9ee2/">View Changes</a></p></div>

2024-04-24T18:36:52.845000Z2024-04-24T18:36:52.845000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/b087645bbcc6915d843745e477563dfff6ca9e8b/

<div class="markdown_content"><p>add configurable scaled-indexed addressing modes<br/><a href="/p/unisimdassembler/code/ci/b087645bbcc6915d843745e477563dfff6ca9e8b/">View Changes</a></p></div>

2024-02-28T20:22:50.694000Z2024-02-28T20:22:50.694000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/055962a6625e0873573ff04b32de512995c1fe61/

<div class="markdown_content"><p>clean up signed/unsigned SIMD converters<br/><a href="/p/unisimdassembler/code/ci/055962a6625e0873573ff04b32de512995c1fe61/">View Changes</a></p></div>

2024-02-28T20:22:50.667000Z2024-02-28T20:22:50.667000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/9d2ae6bd20410637e0ccbd240e68c9c61ad567f6/

<div class="markdown_content"><p>add unsigned fp-to-int SIMD converters<br/><a href="/p/unisimdassembler/code/ci/9d2ae6bd20410637e0ccbd240e68c9c61ad567f6/">View Changes</a></p></div>

2024-02-21T19:53:14.821000Z2024-02-21T19:53:14.821000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/9d03634771989f0c57ad035f79d96415ba17a063/

<div class="markdown_content"><p>clean up unsigned SIMD converters<br/><a href="/p/unisimdassembler/code/ci/9d03634771989f0c57ad035f79d96415ba17a063/">View Changes</a></p></div>

2024-02-14T20:48:33.747000Z2024-02-14T20:48:33.747000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/5243f02b2e29707d53e948a16ef2b5b53e0dbf3c/

<div class="markdown_content"><p>add unsigned int-to-fp SIMD converters<br/><a href="/p/unisimdassembler/code/ci/5243f02b2e29707d53e948a16ef2b5b53e0dbf3c/">View Changes</a></p></div>

2024-02-14T20:48:33.736000Z2024-02-14T20:48:33.736000ZVectorChiefhttps://sourceforge.net/u/vectorchief/https://sourceforge.net/p/unisimdassembler/code/ci/f43ee37be37191cd19bcc5269d068765daae6e3f/

<div class="markdown_content"><p>rename internal Te<strong> registers to TE</strong> on RISCs<br/><a href="/p/unisimdassembler/code/ci/f43ee37be37191cd19bcc5269d068765daae6e3f/">View Changes</a></p></div>